Nonvolatile semiconductor memory cells permitting charge storage capability are well known in the art. The charges are typically stored in a floating gate to define the states of a memory cell. Typically, the states can be either two levels or more than two levels (for multi-level states storage). Mechanisms such as channel hot electron injection (CHEI), source-side injection (SSI), Fowler-Nordheim tunneling (FN), and Band-to-Band Tunneling (BTBT) induced hot-electron-injection can be used to alter the states of such cells in program and/or erase operations. Examples on employing such mechanisms for memory operations can be seen in cell structures in U.S. Pat. Nos. 4,698,787, 5,029,130, 5,792,670, 5,146,426, 5,432,739 and 5,966,329.
All the above mechanisms and cell structures, however, have poor injection efficiency (defined as the ratio of number of carriers collected by the floating gate to the number of carriers supplied). Further, these mechanisms and cell structures require high voltages to support the memory operation, and voltage as high as 10V is often seen. It is believed that the high voltage demands stringent control on the quality of the insulator surrounding the floating gate. The memories operated under these mechanisms thus are vulnerable to manufacturing and reliability problems.
In light of the foregoing problems, it is an object of the present invention to provide improved cell structures that can be operated to enhance carrier injection efficiency and to reduce operation voltages. It is another object of the present invention to provide charge carriers (electrons or holes) transporting with tight energy distribution and high injection efficiency. Other objects of the inventions and further understanding on the objects will be realized by referencing to the specifications and drawings.